1. Field of the Invention
The present invention relates to flash memory. More particularly, the present invention relates to an apparatus and method for controlling flash memory operations.
2. Art Background
One type of prior non-volatile semiconducted memory is the flash electrically erasable programmable read-only memory ("flash"). The flash memory can be programmed with electrical signals and once programmed the flash memory retains its data until erased. After erasure, the flash memory may be programmed with new code or data.
Flash memories differ from conventional electrically erasable programmable read-only memory ("EEPROM") with respect to erasure. Conventional EEPROMs typically use the select transistor for individual byte erasure control. Flash memories, on the other hand, typically achieve much higher density with single transistor cells. During one prior art flash memory erase method, a high voltage is supplied to the sources of every memory cell in a memory array simultaneously. This results in a full array erasure. Typically a logical one means that few if any electrons are stored on a floating gate associated with a bit cell. Logical zero means that many electrons are stored on the floating gate associated with the bit cell. Erasure of the flash memory causes a logical one to be stored in each bit cell. Each single bit cell of that flash memory cannot be overwritten from a logical zero to a logical one without a prior erasure. Each single bit cell of that flash memory can however be overwritten from the logical one to a logical zero, given that this entails simply adding electrons to a floating gate that contains the intrinsic number of electrons associated with the erased state.
The process for erasure, programming and verification requires careful control of the voltages required to perform those steps. For example, one prior art flash memory is the 28F256 complimentary metal oxide semiconductor ("CMOS") flash memory sold by Intel Corporation of Santa Clara, Calif., which is a 256 kilobit flash memory. To control the flash memory, the memory includes a command register to manage electrical erasure and reprogramming. Commands are written for erasure from a controlling microprocessor using standard microprocessor write timings. The command register contents serve as input to an internal state machine that controls erasure and programming circuitry.
Due to increased densities of flash memory, the applications which include a flash memory have also increased. These applications vary dramatically and frequently require different processing and control mechanisms. Typically the applications are driven by a microprocessor coupled to the flash memory via a bus. However, if the overhead at the microprocessor is significant, flash processing throughput decreases. Furthermore, to ensure proper reliable operation of the flash memory, the erasure procedure should be strictly followed. Thus, the use of the microprocessor to control the flash memory over the bus and the interface of the user with the flash memory via the microprocessor increases the likelihood of flash error caused by, for example, over-erasure of the flash memory, due to ill-timed control signals caused by an interrupt or other operation which temporarily halts control signals being issued by the microprocessor.
In addition, it is typical that only one operation can be performed at a time at the flash memory. Thus if a low priority operation is executing and a higher priority operation is to be executed, the higher priority operation must wait for the lower priority operation to complete before the operation can be executed.
Furthermore, as the cost of flash memory decreases, the number of applications which utilize flash memory increases. Therefore, it is desirable to provide a flash memory and interface which is flexible and readily adaptable to a variety of applications.